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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.4
- 발행연도
- 2011.12
- 수록면
- 238 - 246 (9page)
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초록· 키워드
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A 3-5 GHz UWB radar chip in 0.13 ㎛ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. UWB RADAR ARCHITECTURE
Ⅲ. CIRCUIT DESIGN
Ⅳ. MEASURED RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGEMENTS
REFERENCES
참고문헌 (7)
참고문헌 신청
1. [학술지(정기간행물)] - H. Xie / 2010 / A 52- mW 3.1-10.6-GHz Fully Integrated Correlator for IR-UWB Transceivers in 0.18 μm CMOS / IEEE Trans. Industrial Electronics 57 (5) : 1546 ~ 1554
2. [학술대회논문] - S.M. Louwsma / 2007 / A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR / in Proc. IEEE Custom Integrated Circuits Conf.(CICC) : 329 ~ 332
3. [학술대회논문] - T. Sato / 2004 / 4-Gb/s track and hold circuit using parasitic capacitance canceller / Eur. Solid- State Circuits Conf.(ESSCIRC) : 347 ~ 350
4. [학술대회논문] - M. Okushima / 2009 / A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS / in Proc. IEEE Radio Frequency Integrated Circuits(RFIC) Symp : 295 ~ 298
5. [학술지(정기간행물)] - J. Borremans / 2008 / Low-area active-feedback lownoise amplifier design in scaled digital CMOS / IEEE J. Solid-State Circuits 43 (11) : 2422 ~ 2432
2. [학술대회논문] - S.M. Louwsma / 2007 / A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR / in Proc. IEEE Custom Integrated Circuits Conf.(CICC) : 329 ~ 332
3. [학술대회논문] - T. Sato / 2004 / 4-Gb/s track and hold circuit using parasitic capacitance canceller / Eur. Solid- State Circuits Conf.(ESSCIRC) : 347 ~ 350
4. [학술대회논문] - M. Okushima / 2009 / A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS / in Proc. IEEE Radio Frequency Integrated Circuits(RFIC) Symp : 295 ~ 298
5. [학술지(정기간행물)] - J. Borremans / 2008 / Low-area active-feedback lownoise amplifier design in scaled digital CMOS / IEEE J. Solid-State Circuits 43 (11) : 2422 ~ 2432
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UCI(KEPA) : I410-ECN-0101-2013-569-001351307