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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 601 - 604 (4page)
이용수
초록· 키워드
오류제보하기
Artificial neural networks (ANNs) are widely used in various applications such as recognition, security, computer learning and so on. A two hidden layers Back-Propagation ANN (BP-ANN) is a typical one. But BP-ANNs are hard to be implemented in hardware due to interconnections and cost. Recently, Networkson-Chips (NoCs) where a packet-based network is used routing on-chip signals, have begun to attract as a smart structure to solve the interconnect problem. It can also map one or more logical units into a single physical hardware unit and connect with on router.
In this paper we propose a system with NoCs structure to mapping 5 neurons in one router for the two hidden layers BP-ANNs. Our system is evaluated for the latency and throughput using NIRGAM NoCs simulator, and is implemented on an FPGA device to estimate system performance and power consumption. Experimental results show that our proposed system has a great reduction in communication load, low latency and a high throughput. It is also reconfigurable and expandable to meet various NN application problems, and besides, not only BP-ANNs but also a random-connected ANNs or any type ANNs can be implemented in the system by adjusting a routing algorithm of NoC.
In this paper we propose a system with NoCs structure to mapping 5 neurons in one router for the two hidden layers BP-ANNs. Our system is evaluated for the latency and throughput using NIRGAM NoCs simulator, and is implemented on an FPGA device to estimate system performance and power consumption. Experimental results show that our proposed system has a great reduction in communication load, low latency and a high throughput. It is also reconfigurable and expandable to meet various NN application problems, and besides, not only BP-ANNs but also a random-connected ANNs or any type ANNs can be implemented in the system by adjusting a routing algorithm of NoC.
목차
Abstract
1. Two hidden layers BP-ANNs algorithm
2. NoC structure for BP-ANNs
3. Evaluation of this system
4. FPGA Implementation and Conclusions
Acknowledgement
References
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