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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2011.12
- 수록면
- 2,281 - 2,285 (5page)
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초록· 키워드
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An algorithm for extracting SPICE MOS level 2 model parameters for the high voltage MOSFET DC model is proposed. The optimization method for analyzing the nonlinear data of the current-voltage curve using the Gauss-Newton algorithm is proposed and the pre-process step for calculating the threshold voltage and the mobility is proposed. The drain current obtained from the proposed method shows the maximum relative error of 5.6% compared with the drain current of 2-dimensional device simulation for the high voltage MOSFET.
목차
Abstract
1. 서론
2. SPICE MOS level2 DC 모델파라미터 추출 알고리즘
3. 결과 및 고찰
4. 결론
참고문헌
저자소개
참고문헌 (14)
참고문헌 신청
1. [단행본] - A. Amerasekera / 1995 / ESD in Silicon Integrated Circuits / John Wiley & Sons
2. [학술지(정기간행물)] - L.L.Spina / 2009 / Influence of Concurrent Electrothermal and Avalanche Effects on the Safe Operating Area of Multifinger Bipolar Transistors / IEEE Trans. on Electron Devices 56 (3) : 483 ~ 491
3. [단행본] - H. Ballan / 1999 / High Voltage Devices and Circuits in Standatd CMOS Technologies / Kluwer Academic Pub : 181 ~ 226
4. [단행본] - Palo Antognetti / 1986 / Power Integrated Circuits: Physics, Design, and Applications / McGraw-Hill Book Co : 327 ~ 334
5. [학술지(정기간행물)] - Fei Li / 2006 / A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin SiO2 and High-k Gate Stacks / IEEE Trans. on Electron Devices 53 (9) : 2118 ~ 2127
2. [학술지(정기간행물)] - L.L.Spina / 2009 / Influence of Concurrent Electrothermal and Avalanche Effects on the Safe Operating Area of Multifinger Bipolar Transistors / IEEE Trans. on Electron Devices 56 (3) : 483 ~ 491
3. [단행본] - H. Ballan / 1999 / High Voltage Devices and Circuits in Standatd CMOS Technologies / Kluwer Academic Pub : 181 ~ 226
4. [단행본] - Palo Antognetti / 1986 / Power Integrated Circuits: Physics, Design, and Applications / McGraw-Hill Book Co : 327 ~ 334
5. [학술지(정기간행물)] - Fei Li / 2006 / A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin SiO2 and High-k Gate Stacks / IEEE Trans. on Electron Devices 53 (9) : 2118 ~ 2127
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UCI(KEPA) : I410-ECN-0101-2013-560-001078380