지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.5
- 수록면
- 2,899 - 2,905 (7page)
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초록· 키워드
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A synchronous rectification in high performance converter design is an essential block for low voltage and high current applications since significant efficiency and power density improvements can be achieved by replacing schottky rectification with synchronous rectification MOSFETs. Many critical parameters for synchronous rectification MOSFETs and even parasitic components in devices and printed circuit board directly affect to system efficiency of synchronous rectifications. Optimization of the MOSFETs plays an important role in improving efficiency of synchronous rectification. This paper shows the impact of power MOSFET parameters and parasitic inductance on efficiency of synchronous rectification through loss analysis of power MOSFET from an experiment and a simulation results.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. LOW & MEDIUM VOLTAGE MOSFET TECHNOLOGIES
Ⅲ. POWER LOSSES IN SYNCHRONOUS RECTIFICATION
Ⅳ. PARASITIC INDUCTANCE EFFECTS
Ⅴ. CONCLUSION
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UCI(KEPA) : I410-ECN-0101-2013-560-000302912