지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.4
- 수록면
- 18 - 22 (5page)
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초록· 키워드
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In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories for the purpose of allowing for repair in the presence of defective cells or bit lines. In many cases, the repair process will not use all spare columns. Schemes are proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in SEC-DED. These additional check bits increase the dimensions of the H-matrix. The increased number of 1s in the H-matrix increases not only the area overhead but also the delay of the whole system. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area over head and delay.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Proposed Method for Check Bit Addition
Ⅲ. Proposed Logic Sharing Method
Ⅳ. Experiment results
Ⅴ. Conclusion
Ⅵ. Acknowledgements
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UCI(KEPA) : I410-ECN-0101-2013-569-000249515