지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.2
- 발행연도
- 2011.6
- 수록면
- 95 - 103 (9page)
이용수
초록· 키워드
오류제보하기
This paper proposes a 6b 1.2 GS/s 47.8 ㎽ 0.17 ㎟ 65 ㎚ CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 V<SUB>p-p</SUB> at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 ㎚ CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 ㏈ and a maximum SFDR of 44.7 ㏈ at 1.2 GS/s. The ADC with an active die area of 0.17 ㎟ consumes 47.8 ㎽ at 1.2 V and 1.2 GS/s.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED ADC ARCHITECTURE
Ⅲ. CIRCUIT IMPLEMENTATION
Ⅳ. PROTOTYPE ADC MEASUREMENTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGEMENTS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-000410743