지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
초록· 키워드
오류제보하기
A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 ㎓ charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5㎂ current mismatch in CP. It was designed in a standard 0.13㎛ CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38㎽ with 1.5V power supply and effective area is 0.1804㎟.
목차
Abstract
1. 서론
2. 제안한 카운터를 이용한 디지털 보상 기법
3. 실험 결과
4. 결론
감사의 글
참고문헌
저자소개
참고문헌 (6)
참고문헌 신청
B. Razavi / 2001 / Design of Analog CMOS Integrated Circuits / MCgraw-Hill
T. A. D. Riley / 2003 / Techniques for in-band phase noise reduction in ΣΔ synthesizers / IEEE Transactions on Circuits and Systems-Ⅱ, Analog Digital Signal Processing 50(11):794~803
W. Rhee / 1999 / Design of high-performance CMOS charge pumps in phase-locked loops / Proceeding IEEE International Symposium on Circuits and Systems :545~548
Y.-S. Choi / 2006 / Gain-boosting charge pump for current matching in phase-locked loop / IEEE Transactions on Circuits Systems.Ⅱ, Express Briefs 53(10):1022~1025
N. D. Dalt / 2003 / sub-picosecond jitter PLL for clock generation in 0.12μm digital CMOS / IEEE Journal of Solid-State Circuits 38(7):1275~1278
T. A. D. Riley / 2003 / Techniques for in-band phase noise reduction in ΣΔ synthesizers / IEEE Transactions on Circuits and Systems-Ⅱ, Analog Digital Signal Processing 50(11):794~803
W. Rhee / 1999 / Design of high-performance CMOS charge pumps in phase-locked loops / Proceeding IEEE International Symposium on Circuits and Systems :545~548
Y.-S. Choi / 2006 / Gain-boosting charge pump for current matching in phase-locked loop / IEEE Transactions on Circuits Systems.Ⅱ, Express Briefs 53(10):1022~1025
N. D. Dalt / 2003 / sub-picosecond jitter PLL for clock generation in 0.12μm digital CMOS / IEEE Journal of Solid-State Circuits 38(7):1275~1278
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UCI(KEPA) : I410-ECN-0101-2012-560-004009883