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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 46 - 52 (7page)
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초록· 키워드
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The purpose of this paper is to propose the methodology of Low-Power circuit design in the aspect of the architecture and circuit level. Recently, more rapid computations are very important event in DSP, image processing and multi-purpose processor. So, it is very important to reduce power consumption in digital circuits and to maintain computational throughput. In this reason, Design experience and research in the early 190s has demonstrated that doing so requires a “power conscious” design methodology that addresses dissipation at every level of the design hierarchy. Evidently many pass transistor logic are proposed for reducing the power consumption and circuit size. In this paper, we introduce the methodologies for low-power using pass-transistor and SSD (Signal Dependency Diagram) technique for parallel and pipelined architecture.
목차
Abstract
1. Introduction
2. Basic analysis of power dissipation
3. Pass-Transistor logic
4. Design methodology for pass-transistor logic
5. Architecture level approach
6. Conclusion
References
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