지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.10 No.4
- 발행연도
- 2010.12
- 수록면
- 282 - 291 (10page)
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초록· 키워드
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This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ㎛ CMOS technology and the die area is 5 ㎜ × 5 ㎜. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 ㏈ and 41 ㏈, respectively. The power consumption of the transmitter and receiver are 160 ㎽ and 250 ㎽ from the supply voltage of 2.5 V, respectively.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. SYSTEM ARCHITECTURE
Ⅲ. BUILDING BLOCKS
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (13)
참고문헌 신청
1. [기타자료] - / 2005 / Asymmetric Digital Subscriber Line (ADSL) Transceivers - Extended Bandwidth ADSL2 (ADSL2+) in ITU-T Recommendation G.992.5
2. [학술대회논문] - S.-S. Lee / 2002 / Integration and system design trends of ADSL analog front ends and hybrid line interfaces / Proc. CICC : 37 ~ 44
3. [학술대회논문] - S. Oswal / 2004 / An integrated ADSL CPE analog front-end in a 0.13 m CMOS SoC / IEEE ISSCC Dig. Tech. Papers : 404 ~ 405
4. [학술대회논문] - R. Hogervorst / 2004 / A 3 V CMOS quad-spectrum ADSL CPE analog front-end with 5 V integrated line driver / IEEE ISSCC Dig. Tech. Papers : 406 ~ 407
5. [학술대회논문] - Y.S. Kim / 2008 / A Design of Full-CMOS VDSL2 Receiver in 0.25 m CMOS process / Proc. ISOCC : 334 ~ 337
2. [학술대회논문] - S.-S. Lee / 2002 / Integration and system design trends of ADSL analog front ends and hybrid line interfaces / Proc. CICC : 37 ~ 44
3. [학술대회논문] - S. Oswal / 2004 / An integrated ADSL CPE analog front-end in a 0.13 m CMOS SoC / IEEE ISSCC Dig. Tech. Papers : 404 ~ 405
4. [학술대회논문] - R. Hogervorst / 2004 / A 3 V CMOS quad-spectrum ADSL CPE analog front-end with 5 V integrated line driver / IEEE ISSCC Dig. Tech. Papers : 406 ~ 407
5. [학술대회논문] - Y.S. Kim / 2008 / A Design of Full-CMOS VDSL2 Receiver in 0.25 m CMOS process / Proc. ISOCC : 334 ~ 337
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UCI(KEPA) : I410-ECN-0101-2012-569-003817144