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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.4 No.3
- 발행연도
- 1999.6
- 수록면
- 398 - 405 (8page)
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초록· 키워드
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This paper describes an automated architectural synthesis system for implementing recursive DSP algorithms specified by graphs. The synthesis approach is based on a synchronous multiprocessor scheduler. The input to the system is a recursive DSP flow graph with the required throughput and latency, and the output is a complete circuit diagram with the associated control signals. The synthesis system first computes optimality conditions for a given input algorithm and finds a schedule which satisfies the optimality conditions. Then the synthesis system modifies the generated schedule so as to minimize the number of resources and translates the optimal schedule into a structural specification including the control structures for a circuit realization. This paper illustrates the synthesis process with an example of a fourth order Wave Digital Filter, and compares our synthesis system with other synthesis systems.
목차
Abstract
Ⅰ. Introduction
Ⅱ. System Overview
Ⅲ. Scheduling
Ⅳ. Circuit Generator
Ⅴ. Comparison with Other Synthesis Systems
Ⅵ. Conclusion
References
저자소개
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