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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE JOUNAL OF SEMICONDUCTOR THCHNOLOGY AND SCIENCE Vol.4 No.3
- 발행연도
- 2004.9
- 수록면
- 168 - 173 (6page)
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초록· 키워드
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A low power CMOS receiver baseband analog circuit based on alternating filter and gain stages reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18 I'm CMOS technolog} and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. OPTIMUM DESIGN METHOD FOR LOW POWER BASEBAND CHAIN
Ⅲ. CHANNEL SELECTION FILTER
Ⅳ. PROGRAMMABLE GAIN AMPLIFIER(PGA)
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
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