지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2001.10
- 수록면
- 708 - 712 (5page)
이용수
초록· 키워드
오류제보하기
A new phase-shifted parallel-input/senes-output (PISO) dual inductor-fed push-pull convener for high-power step-up applications is proposed This converter is operated at a constant duty cycle and employs an auxiliary circuit to control the output voltage with a phase-shift between the two modules It features a voltage conversion characteristic which is linear to changes in the control input, and high step-up ratio with a greatly reduced switch turn-off stress resulting in a significant increase in the converter efficiency It also shows a low ripple content and low root-mean-square (RMS) current in the output capacitor The operational principle is analyzed and a comparative analysis with the conventional pulse-width-modulated (PWM) PISO dual inductor-fed push-pull converter is presented. A 50kHz, 800W, 3S0Vdc prototype with an input of 20-32Vdc has also been constructed to validate the proposed converter. The proposed converter compares favorably with the conventional counterpart and is considered well suited to high-power step-up applications.
목차
Abstract
Ⅰ.INTRODUCTION
Ⅱ.OPERATIONAL PRINCIPLES
Ⅲ.FEATURES AND COMPARATIVE ANALYSIS
Ⅳ.EXPERIMENTAL RESULTS
Ⅴ.CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2009-560-014238119