Redundant Binary 연산을 이용한 고속 복소수 승산기 ( A High - Speed Complex Multiplier based on Redundant Binary Arithmetic )

신경욱

전자공학회논문지-C

1997 .02

Redundant Binary 구조를 이용한 16 ×16-bit 승산기 ( An 16 × 16-bit Multiplier with Redundant Binary Architecture )

김태민 ,  신건순

대한전자공학회 학술대회

1997 .01

Low-Power / High-Speed Redundant Binary Complex-Number Multiplier-Accumulator ( CMAC )

Ho Ha Kim ,  Kyung Wook Shin

ICVC : International Conference on VLSI and CAD

1997 .01

VLSI Design of High-Performance Floating-Point Multiplier

Byeong Yoon Choi

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1994 .01

A Design of High Speed Adder Circuit Using Redundant Binary Code

Ig Kyun Kim ,  Jin Jong Cha ,  Kyung Soo Kim

ICVC : International Conference on VLSI and CAD

1997 .01

여유자유도를 가진 로보트의 Pre-Multiplier 모델에 관한 연구 ( A Study on the Pre-Multiplier Model for Redundant Manipulator )

정완균 ,  김진오 ,  P. Khosla

대한전자공학회 학술대회

1989 .01

여유자유도를 가진 로보트의 Pre-multiplier 모델에 관한 연구

정완균 ,  김진오 ,  P. Khosla

제어로봇시스템학회 국내학술대회 논문집

1989 .10

Efficient Semi-Systolic Finite Field Multiplier Using Redundant Representation

Kee-Won Kim ,  Hyun-Ho Lee ,  Seung-Hoon Kim

Proceedings of The International Workshop on Future Technology

2017 .07

An Ultimate Performance Binary Multiplier by Reduced Carry Generation and Propagation

Jun Rim Choi ,  Jong Chuck Jung ,  Kyu Sun Lee

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1996 .01

Multiplier 합성

한탁돈

대한전자공학회 기타 간행물

1992 .01

Redundant Binary 복소수 필터를 이용한 적응 결정귀환 등화기 모듈 설계

김호하 ,  안병규 ,  신경욱

대한전자공학회 학술대회

1998 .11

Redundant Binary 복소수 필터를 이용한 적응 결정귀환 등화기 모듈 설계 ( A Design of Adaptive Decision-Feedback Equalizer Module using Redundant Binary Complex Filter )

김호하 ,  안병규 ,  신경욱

대한전자공학회 학술대회

1998 .11

Redundant Binary 수치계를 이용한 radix-2 SRT 부동 소수점 제산기 유닛 설계

이종남 ,  신경욱

한국정보통신학회논문지

2001 .06

A Design of 16×16-bit Redundant Binary MAC Using 0.25㎛ CMOS Technology

Tae-Min Kim ,  Gun-Soon Shin

한국정보통신학회논문지

2003 .03

Binary Decision Tree를 이용한 형상 인식 알고리즘 ( A New Object Recognition Algorithm Using Binary Decision Tree Classifier )

김병무 ,  이정환 ,  김성대 외 1명

대한전자공학회 학술대회

1986 .01

3직 Rate Multiplier의 설계 ( On the Design Methods of Ternary Rate Multiplier )

황인호 ,  심수보

한국통신학회지(정보와통신)

1981 .01

Design of High speed 16x16 Multiplier Using by Multi Input Compressor

Hun-yong Lim ,  Jin-ku Kang

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2004 .07

Implementation of High-speed multiplier Using Multi-Valued Logic circuit

Hong-Bok Song ,  Jin-Woo Pa ,  k 외 1명

ICEIC : International Conference on Electronics, Informations and Communications

1998 .08

Implementation of High-Speed Multiplier Using Multi-Valued Logic Circuit

Hong Bok Song ,  Jin Woo Pa ,  k 외 1명

ICEIC : International Conference on Electronics, Informations and Communications

1998 .01

Redundant Fault Characterization of Speed Independent Circuits

Eun Jung Oh ,  Dong Ik Lee

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1998 .01